This paper explains how a PCIe switch supports lane-rate conversion, allowing data received on one port at a given PCIe generation and lane width to be retransmitted on another port operating at a different rate. The paper first reviews PCIe fundamentals, including link training, where link width and speed are negotiated independently per port, and describes the PCIe layered packet structure. Within the layered packets the Transaction Layer Packets (TLPs), which contain the payload and headers, are created once by the source device and remain unchanged across the fabric, while Data Link Layer (DLL) and Physical Layer information are removed and regenerated at every hop. The physical layer’s role in encoding the data into electrical signals and in using lane striping is also described, as these determine the effective throughput. Using this background information, the paper explains that when the switch receives a packet it strips the incoming DLL and physical layer encoding, buffers the TLP, and then retransmits it on the outgoing port with newly generated DLL and physical layer signaling appropriate for that link. This allows the switch to bridge links with different speeds and widths (e.g., Gen3 x16 to Gen4 x8) without modifying the payload or requiring manual configuration.
